//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module SOH4_MPI(
   input                         SOH4_RESET,

   input                         MPI_CLK,
   input[8:0]                    MPI_ADDR,
   input                         MPI_CS,
   input                         MPI_WE,
   input[15:0]                   MPI_WD,
   output reg[15:0]              MPI_RD,

   output[4:0]                   MPI_OBSID_ADDR,
   output                        MPI_OBSID_WE,
   output[7:0]                   MPI_OBSID_WD,
   input[7:0]                    MPI_OBSID_RD,

   output                        MPI_OBSIA_WE,
   output[8:0]                   MPI_OBSIA_WD,
   output[6:0]                   MPI_OBSIA_ADDR,
   input[8:0]                    MPI_OBSIA_RD,

   output                        DEBUG_0
   );


// ++++++++++++++++++             Section 0: Address Map Table          ++++++++++++++++++  //
// 0x0000            Module Version
// 0x0100-0x011F     the bytes map table for drop side overhead bytes serial interface



// drop side overhead bytes map table
  assign MPI_OBSID_ADDR[4:0]         = MPI_ADDR[4:0];
  assign MPI_OBSID_WE                = ( MPI_WE==1'b1 && MPI_ADDR[8:5]==4'b1_000 && MPI_CS==1'b1 );
  assign MPI_OBSID_WD[7:0]           = MPI_WD[7:0];

  // add side overhead bytes map
  assign MPI_OBSIA_WE                = ( MPI_WE==1'b1 && MPI_ADDR[8:7]==2'b1_1 && MPI_CS==1'b1 );
  assign MPI_OBSIA_WD[8:0]           = MPI_WD[8:0];
  assign MPI_OBSIA_ADDR[6:0]         = MPI_ADDR[6:0];

//always @( posedge MPI_CLK or posedge SOH4_RESET) begin
// if ( SOH4_RESET==1'b1 )
//    MPI_RD[15:0]                           <= 16'd0;
// else begin
//    if ( MPI_WE==1'b1 && MPI_CS==1'b1 
// end
//end

always @( posedge MPI_CLK or posedge SOH4_RESET) begin
   if ( SOH4_RESET==1'b1 )
      MPI_RD[15:0]                           <= 16'd0;
   else begin
      if ( MPI_CS==1'b1 && MPI_ADDR[8:5]==4'b1_000 ) begin         // 0x0100-0x011F
         MPI_RD[15:8]                        <= 8'd0;
         MPI_RD[7:0]                         <= MPI_OBSID_RD[7:0];
      end
      else if ( MPI_CS==1'b1 && MPI_ADDR[8:7]==2'b1_1 ) begin         // 0x0180-0x01FF
         MPI_RD[15:9]                        <= 7'd0;
         MPI_RD[8:0]                         <= MPI_OBSIA_RD[8:0];
      end
      else begin
         case ( MPI_ADDR[8:0] )
         9'h000: MPI_RD[15:0]                <= 16'h1000;
         default:MPI_RD[15:0]                <= 16'h0000;
         endcase
      end
   end
end

  assign DEBUG_0   = MPI_WE==1'b1 && MPI_ADDR[8:0]==9'd1 && MPI_CS==1'b1;


endmodule
